Talk:MTRR

''Note that the reg01 is actually a normal memory layout due to 3G/1G memory split option i have set my kernel up as, There is not section at point reg01 for my write-combined graphics card in fact that is missing all together. This is because the ATI fglrx driver has claimed it. If you use Frame-buffer either kernel or X.org then the setting will appear as reg03,4,5 etc and will be moved(remapped) from the reg01 slot IO hope that clears up the reason and how this setting in the kernel works. If when MTRR_cleanup is disabled you notice the base address of your graphics card is at a different regXX number then change the spare reg number to this accordingly so you can allow for the write-combined or as in my case proprietary driver to take control of it.''

First, why use an edge case as the example? Second, this explains nothing about how to select the correct MTRR cleanup spare reg number.